Field effect transistor structure with self-aligned raised source/drain extensions

ABSTRACT

Field effect transistor structures include a channel region formed in a recessed portion of a substrate. The recessed channel portion permits the use of relatively thicker source/drain regions thereby providing lower source/drain extension resistivity while maintaining the physical separation needed to overcome various short channel effects. The surface of the recessed channel portion may be of a rectangular, polygonal, or curvilinear shape. In a further aspect of the present invention, transistors are manufactured by a process in which a damascene layer is patterned, the channel region is recessed by etch that is self-aligned to the patterned damascene layer, and the gate electrode is formed by depositing a material over the channel region and patterned damascene layer, polishing off the excess gate electrode material and removing the damascene layer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to metal-oxide-semiconductor field effecttransistors (MOSFETs) and more particularly to transistor structureshaving self-aligned raised source/drain regions, and methods of makingsame.

[0003] 2. Background

[0004] The trend of integrating more functions on a single substratewhile operating at ever higher frequencies has existed in thesemiconductor industry for many years. Advances in both semiconductorprocess technology and digital system architecture have aided inproducing these more highly integrated and faster operating integratedcircuits.

[0005] The desired result of many recent advances in semiconductorprocess technology has been to reduce the dimensions of the transistorsused to form the individual circuits found on integrated circuits. Thereare several well-recognized benefits of reducing the size oftransistors. In the case of MOSFETs, reducing the channel lengthprovides the capability to deliver a given amount of drive current witha smaller channel width. By reducing the width and length of a FET, theparasitic gate capacitance, which is a function of the area defined bythe width and length can be reduced, thereby improving circuitperformance. Similarly, reducing the size of transistors is beneficialin that less area is consumed for a given circuit, and this allows morecircuits in a given area, or a smaller, less costly chip, or both.

[0006] It has also been well known that MOSFETs can not simply be scaleddown linearly. That is, as the width and length attributes of a MOSFETare reduced, other parts of the transistor, such as the gate dielectricand the junctions must also be scaled so as to achieve the desiredelectrical characteristics. Undesirable electrical characteristics inMOSFETs due to improper scaling include coupling of the electric fieldinto the channel region and increased subthreshold conduction. Theseeffects are sometimes referred to in this field as short channeleffects.

[0007] A number of methods have been developed to form ever more shallowsource/drain junctions for MOSFETs in order to achieve proper scaling.Unfortunately, these very shallow junctions create source/drainextensions that have increased resistivity as compared with deepersource/drain junctions. In longer channel length MOSFETs with deepersource/drain junctions, the source/drain extension resistivity wasnegligible compared to the on-resistance of the MOSFET itself. However,as MOSFET channel lengths decrease into the deep sub-micron region, theincreased source/drain extension resistivity becomes a significantperformance limitation.

[0008] What is needed is a field effect transistor structure having veryshort channel length and low source/drain extension resistivity, yetoperable to produce high drive currents without suffering from the shortchannel effects that produce significant levels of off-state current.What is further needed is a method of manufacturing such a structure.

SUMMARY OF THE INVENTION

[0009] Briefly, field effect transistor structures include a channelregions formed in a recessed portion of a substrate. The recessedchannel portion permits the use of relatively thicker source/drainregions thereby providing lower source/drain extension resistivity whilemaintaining the physical separation needed to overcome various shortchannel effects.

[0010] In a further aspect of the present invention, the surface of therecessed channel portion may be of a rectangular, polygonal, orcurvilinear shape.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a schematic cross-section of a conventional MOSFETshowing symmetrical source/drains with source/drain extensions.

[0012]FIG. 2 is a schematic cross-section of a MOSFET having raisedsource/drain extension in accordance with a first exemplary embodimentof the present invention

[0013]FIG. 3 is a schematic cross-section of a MOSFET in accordance witha second exemplary embodiment of the present invention having taperededges and raised source/drain extensions.

[0014]FIG. 4 is a schematic cross-section of a MOSFET in accordance witha third exemplary embodiment of the present invention having acurvilinear gate dielectric and raised source/drain extensions.

[0015]FIG. 5 is a schematic cross-section of a wafer having an etch stoplayer and an unpatterned damascene layer formed thereon.

[0016]FIG. 6 is a schematic cross-section showing the structure of FIG.5, after the damascene and etch stop layers have been patterned.

[0017]FIG. 7 is a schematic cross-section showing the structure of FIG.6, after a first spacer layer has been formed adjacent to the sidewallsof the patterned damascene and etch stop layers.

[0018]FIG. 8 is a schematic cross-section showing the structure of FIG.7, after the exposed silicon has been anisotropically etched.

[0019]FIG. 9 is a schematic cross-section showing the structure of FIG.8, after the second spacer has been removed, a gate oxide layer grownover the exposed silicon, and a gate electrode layer deposited over thewafer.

[0020]FIG. 10 is a schematic cross-section showing the structure of FIG.9, after the gate electrode is formed by a chemical mechanical polishingoperation which removes the excess gate electrode material.

[0021]FIG. 11 is a schematic cross-section showing the structure of FIG.10, after the damascene, first spacer, and etch stop layers have beenetched away.

[0022]FIG. 12 is a schematic cross-section showing a completed MOSFETformed from the structure of FIG. 11, after conventional processingoperations such as source/drain extension implants, gate spacerformation, deep source/drain implants, and silicidation of source/drainsand gate electrode.

[0023]FIG. 13 is a schematic cross-section showing the structure of FIG.7, after the exposed silicon has been oxidized, and the exposed oxidizedsilicon has been etched, forming a recess with tapered.

[0024]FIG. 14 is a schematic cross-section showing the structure of FIG.13, after the second spacer has been removed, a gate oxide layer grownover the exposed silicon, and a gate electrode layer deposited over thewafer.

[0025]FIG. 15 is a schematic cross-section showing the structure of FIG.14, after the gate electrode is formed by a chemical mechanicalpolishing operation which removes the excess gate electrode material.

[0026]FIG. 16 is a schematic cross-section showing the structure of FIG.15, after the damascene, first spacer, and etch stop layers have beenetched away.

[0027]FIG. 17 is a schematic cross-section showing a completed MOSFETformed from the structure of FIG. 16, after conventional processingoperations such as source/drain extension implants, gate spacerformation, deep source/drain implants, and silicidation of source/drainsand gate electrode.

[0028]FIG. 18 is a schematic cross-section showing the structure of FIG.7, after the exposed silicon has been isotropically etched.

[0029]FIG. 19 is a schematic cross-section showing the structure of FIG.18, after the second spacer has been removed, a gate oxide layer grownover the exposed silicon, and a gate electrode layer deposited over thewafer.

[0030]FIG. 20 is a schematic cross-section showing the structure of FIG.19, after the gate electrode is formed by a chemical mechanicalpolishing operation which removes the excess gate electrode material.

[0031]FIG. 21 is a schematic cross-section showing the structure of FIG.20, after the damascene, first spacer, and etch stop layers have beenetched away.

[0032]FIG. 22 is a schematic cross-section showing a completed MOSFETformed from the structure of FIG. 21, after conventional processingoperations such as source/drain extension implants, gate spacerformation, deep source/drain implants, and silicidation of source/drainsand gate electrode.

[0033]FIG. 23 is a flow diagram of a process in accordance with thepresent invention.

DETAILED DESCRIPTION

[0034] Overview

[0035] In order to continue to scale the MOSFET to smaller dimensions,it is necessary to scale both the lateral dimensions (e.g., gate length)as well as the vertical dimensions (e.g., junction depth). Inparticular, it is required to reduce the depth of the source/drainextension (SDE) as the dimensions of the MOSFET are scaled down, so asto reduce short channel effects. However, as SDE depth is reduced, theelectrical resistance of this region is increased, thereby reducingtransistor performance. Additionally, transistor performance isadversely affected by the reduction of SDE depth because current throughthe transistor needs to spread out from the thin accumulation layer.

[0036] Simply increasing the SDE depth, that is, its thickness,addresses the series resistance problem at the expense of having totolerate short channel effects that are adverse to increased transistorperformance. Conventional transistor structure engineering has focusedon optimizing the trade-off between SDE depth and transistorperformance, rather than trying to re-engineer the relationship betweenthe thickness of the SDE and role of SDE thickness in inducing undesiredshort channel effects in MOSFETs.

[0037] Elevating the SDE region that is outside gate control, using, forexample, a selective epitaxy process, can reduce the series resistanceto a limited extent. However, because the SDE region under the gate,which is where most of the current spreading takes place, is notaffected, the benefit of elevating the SDE region outside of gatecontrol is of limited value. The elevated (also referred to as raised)SDE typically creates additional undesired gate-to-drain andgate-to-source overlap capacitance.

[0038] MOSFETs in accordance with an exemplary embodiment of the presentinvention include self-aligned, elevated SDE regions. More particularly,as can be seen in FIGS. 2-4, the SDE regions are elevated with respectto the channel region. Because the elevated SDE regions underlie thegate electrode they are affected by the electric field induced by thecharge on the gate electrode. This gate control effectively reduces theseries resistance in the SDE regions. The SDEs in MOSFETs that embodythe present invention can have increased thickness, relative toconventional MOSFETs, to reduce series resistance because the portion ofthe SDE that protrudes below the recessed central channel region isshallow, and therefore short channel effects are reduced. Furthermore,because the elevated SDE in accordance with the present invention isself-aligned to the gate electrode, overlap capacitance is reducedrelative to conventional raised SDE structures.

[0039] Terminology

[0040] The terms, chip, integrated circuit, monolithic device,semiconductor device or component, and microelectronic device orcomponent, and similar expressions are often used interchangeably inthis field. The present invention is applicable to all the above as theyare generally understood in the field.

[0041] The term “gate” is context sensitive and can be used in two wayswhen describing integrated circuits. As used herein, gate refers to theinsulated gate terminal, also referred to as a gate electrode, of athree terminal FET when used in the context of transistor circuitconfiguration, and refers to a circuit for realizing an arbitrarylogical function when used in the context of a logic gate. A FET can beviewed as a four terminal device when the semiconductor body isconsidered.

[0042] Polycrystalline silicon is a nonporous form of silicon made up ofrandomly oriented crystallites or domains. Polycrystalline silicon isoften formed by chemical vapor deposition from a silicon source gas orother methods and has a structure that contains large-angle grainboundaries, twin boundaries, or both. Polycrystalline silicon is oftenreferred to in this field as polysilicon, or sometimes more simply aspoly.

[0043] Source/drain terminals refer to the terminals of a FET, betweenwhich conduction occurs under the influence of an electric field,subsequent to the inversion of the semiconductor surface under theinfluence of an electric field resulting from a voltage applied to thegate terminal. Source/drain terminals are typically formed in asemiconductor substrate and have a conductivity type (i.e., p-type orn-type) that is the opposite of the conductivity type of the substrate.Sometimes, source/drain terminals are referred to as junctions.Generally, the source and drain terminals are fabricated such that theyare geometrically symmetrical. Source/drain terminals may includeextensions, sometimes referred to as tips, which are shallower thanother portions of the source/drain terminals. The tips typically extendtoward the channel region of a FET, from the main portion of thesource/drain terminal. With geometrically symmetrical source and drainterminals it is common to simply refer to these terminals assource/drain terminals, and this nomenclature is used herein. Designersoften designate a particular source/drain terminal to be a “source” or a“drain” on the basis of the voltage to be applied to that terminal whenthe FET is operated in a circuit.

[0044] Substrate, as used herein, refers to the physical object that isthe basic workpiece that is transformed by various process operationsinto the desired microelectronic configuration. A substrate may also bereferred to as a wafer. Wafers, may be made of semiconducting,non-semiconducting, or combinations of semiconducting andnon-semiconducting materials.

[0045] The term vertical, as used herein, means substantiallyperpendicular to the surface of a substrate.

[0046] A schematic cross-section of a conventional FET is shown inFIG. 1. More particularly, as shown in FIG. 1, a substrate 102 has agate dielectric layer 111 disposed over the surface thereof, and apatterned gate electrode is formed over gate dielectric layer 104wherein the gate electrode has a polysilicon portion 108 and a silicidedportion 107. As shown, sidewall spacers 110 are disposed along laterallyopposed sidewalls of the gate electrode. In this example of aconventional FET, substrate 102 is a silicon wafer, and gate dielectriclayer 104 is a silicon dioxide layer.

[0047] Structural Examples

[0048] FIGS. 2-4 show several illustrations of transistor structureswhich embody the present invention.

[0049]FIG. 2 shows a schematic cross-section of a MOSFET 200illustrating one embodiment of the present invention. MOSFET 200includes a gate dielectric 211 disposed over a portion of wafer 102. Itcan be seen that, unlike the conventional MOSFET of FIG. 1, gatedielectric 211 conforms to a recess in wafer 102. The recess has abottom portions and substantially vertical sidewalls. A gate electrodeis formed over gate dielectric 211, the gate electrode having apolysilicon portion 208 and a silicide portion 107. Sidewall spacers110, typically silicon nitride, are disposed adjacent the gateelectrode. Source/drain extensions 205 are disposed adjacent gatedielectric 211, and deep source/drain regions 204 are disposedsubstantially wafer 102 in a self-aligned fashion with respect tospacers 110. The spatial relationship between deep source/drain regions204, source/drain extensions 205 and the channel region underlying gatedielectric 211, are important in providing the electrical advantages ofthe present invention. By providing transistor 200 with a recessedchannel region, source/drain extensions 205 may be elevated with respectthereto. In turn, by elevating source/drain extensions 205, they may bemade thicker for reduced electrical resistivity, while appearing to bescaled down in thickness relative to their relationship with the channelregion. Also, the innermost portions of source/drain extensions 205,i.e., the portions nearest to the channel region, have a portion of thegate electrode overlying them. This arrangement is also believed toprovide improvements in electrical performance.

[0050]FIG. 3 shows a schematic cross-section of a MOSFET 300illustrating an alternative embodiment of the present invention. MOSFET300 includes a gate dielectric 311 disposed over a portion of wafer 102.It can be seen that, unlike the conventional MOSFET of FIG. 1, gatedielectric 311 conforms to a recess in wafer 102. The recess has abottom portions and tapered sidewalls. Typically, these taperedsidewalls form an angle greater than 90° with respect to the bottomportion of the recess. A gate electrode is formed over gate dielectric311, the gate electrode having a polysilicon portion 308 and a silicideportion 107. Sidewall spacers 110, typically silicon nitride, aredisposed adjacent the gate electrode. Source/drain extensions 305 aredisposed adjacent gate dielectric 311, and deep source/drain regions 304are disposed substantially wafer 102 in a self-aligned fashion withrespect to spacers 110. The spatial relationship between deepsource/drain regions 304, source/drain extensions 305 and the channelregion underlying gate dielectric 311, are important in providing theelectrical advantages of the present invention. By providing transistor300 with a recessed channel region, source/drain extensions 305 may beelevated with respect thereto. In turn, by elevating source/drainextensions 305, they may be made thicker for reduced electricalresistivity, while appearing to be scaled down in thickness relative totheir relationship with the channel region.

[0051]FIG. 4 shows a schematic cross-section of a MOSFET 400illustrating another alternative embodiment of the present invention.MOSFET 400 includes a gate dielectric 411 disposed over a portion ofwafer 102. It can be seen that, unlike the conventional MOSFET of FIG.1, gate dielectric 411 conforms to a recess in the wafer 102. The recesshas a curvilinear surface. A gate electrode is formed over gatedielectric 411, the gate electrode having a polysilicon portion 408 anda silicide portion 107. Sidewall spacers 110, typically silicon nitride,are disposed adjacent the gate electrode. Source/drain extensions 405are disposed adjacent gate dielectric 411, and deep source/drain regions404 are disposed substantially wafer 102 in a self-aligned fashion withrespect to spacers 110. The spatial relationship between deepsource/drain regions 404, source/drain extensions 405 and the channelregion underlying gate dielectric 411, are important in providing theelectrical advantages of the present invention. By providing transistor400 with a recessed channel region, source/drain extensions 405 may beelevated with respect thereto. In turn, by elevating source/drainextensions 405, they may be made thicker for reduced electricalresistivity, while appearing to be scaled down in thickness relative totheir relationship with the channel region.

[0052] Many variations are possible within the scope of the presentinvention. For example, gate dielectric layer 104 is typically a thinlayer of oxidized silicon, but the thickness and chemical make-up ofgate dielectric layer 104 may be varied within the scope of theinvention. Similarly, it will be clear to those skilled in the art, thatsilicide layers 106, 107 may be formed from various metals, includingbut not limited to, titanium, tungsten, nickel, cobalt, and molybdenum;and silicide layers 106, 107 are not required to be of the same materialor the same thickness. In further alternatives, transistors inaccordance with the present invention may be formed without silicidelayers, and may further be formed with metal gate electrodes rather thanpolysilicon gate electrodes. Sidewall spacers 110 are typically formedof silicon nitride, but other suitable materials may be substituted, andthe sidewall spacers may be comprised of more than one layer ofmaterial. In still further alternatives; the transistor may be formedwith silicon germanium source/drain terminals. The foregoing descriptionof alternative materials and structures is for illustrative purposesonly, and is not intended as an exhaustive list of alternatives. Thoseskilled in the art will undoubtedly recognize further variations withinthe scope of the invention.

[0053] Process Examples

[0054] Processes embodying the present invention include a damascenetransistor flow coupled with a self-aligned channel recess etch. Nospecial equipment, other than that typically used for producing MOSintegrated circuits is required. In typical embodiments, channel implantoperations are performed on a silicon wafer in a conventional manner, anetch stop layer, typically silicon dioxide, and a damascene layer,typically silicon nitride, are then formed over the wafer. The damascenelayer is then patterned using a reverse tone polysilicon (i.e., gateelectrode) mask. Alternatively the damascene layer is patterned usingthe conventional polysilicon mask with a negative photoresist. Thepatterning of the damascene layer results in openings being formed inareas where the gate electrodes are to be formed. Typically, the etchstop layer at the bottom of the damascene layer opening is removed, anda first spacer may then be formed along the sidewalls of the openings inthe damascene layer. These first spacers define regions of the channelthat will be recessed. Several alternative processes for recessing thechannel are available. For example, in one embodiment an anisotropicetch (e.g., dry etch) of the exposed silicon is performed to recess thetransistor channel region. In another embodiment, the exposed silicon isfirst oxidized, and the oxide is then etched, resulting in a recess witha tapered, rather than vertically abrupt, transition edge. In a furtheralternative embodiment, the channel recess etch is performed using anisotropic etch (e.g., wet etch) of the exposed silicon, which results ina curvilinear shape for the channel recess. IN relation to the recessedchannel, the source/drain extension are elevated.

[0055] After the channel recess operation, a gate dielectric, typicallyan oxide of silicon, is formed over the surface of the channel recess. Amaterial, such as, but not limited to, polysilicon, may then bedeposited over the surface of the wafer. A planarization operation,typically chemical mechanical polishing using the damascene layer as anetch stop, is then performed. The damascene and underlying etch stoplayers are then removed and source/drain extensions are formed,typically by ion implantation. Spacers are then formed along laterallyopposed sidewalls of the gate electrodes. These spacers are oftenreferred to as sidewall spacers. Deep source/drain regions are thenformed, aligned to the sidewall spacers, typically by ion implantation.

[0056] Further description of illustrative processes embodying thepresent invention are provided below in connection with FIGS. 5-22.

[0057] A first process embodying the present invention is described inconjunction with FIGS. 5-12. Referring to FIG. 5, a silicon wafer 102has an etch stop layer 502 formed thereon. Etch stop layer 502 istypically, but not required to be an oxide of silicon. Etch stop layer502 may be formed by thermal oxidation of the surface of wafer 102, orby well-known deposition processes. A layer 504, referred to hereinafteras a damascene layer, is formed over etch stop layer 502. Damascenelayer 504 is typically a deposited layer of silicon nitride.

[0058] After deposition, damascene layer 504 is patterned, so as to formopenings therein. Patterning is typically performed with well-knownphotolithography processes. The openings in damascene layer 504 havesubstantially vertical sidewalls, but this is not a requirement of thepresent invention. These openings correspond to the locations oftransistor gate electrodes which are to be formed in a later stage ofthe process. The openings in damascene layer 604 expose portions ofunderlying etch stop layer 502. The exposed portions of etch stop layer502 is removed to expose the underlying silicon wafer 102. FIG. 6 showsthe structure of FIG. 5 after the patterning of layers 504 and 502.

[0059] Referring to FIG. 7, the structure of FIG. 6 is shown after twosets of spacers have been formed adjacent the vertical sidewalls of theopenings in layers 504, 502. A first spacer 508 is formed immediatelyadjacent to the sidewalls of the openings and a second spacer 510 isformed adjacent first spacer 508, as shown in FIG. 7. First spacer 508is typically formed from silicon nitride which has been deposited by CVDand then subjected to an anisotropic etch. Second spacer 510 istypically formed from silicon dioxide which has been deposited by CVDand then subjected to an anisotropic etch.

[0060]FIG. 8 shows the structure of FIG. 7 after a recess 512 is formedin wafer 102. The recess in the wafer 102 is formed by an anisotropicetch process (e.g., dry etching of silicon). Recess 512 has a bottomportion 514 and substantially vertical sidewalls 516.

[0061] Subsequent to formation of recess 512, second spacer 510 isremoved, the exposed silicon surface is oxidized to form a gatedielectric layer 511, and polysilicon 518 is deposited over the surfaceof wafer 102 as shown in FIG. 9. Those skilled in the art and having thebenefit of this disclosure will recognize, that gate dielectric layer511 may be formed in other ways or with other materials. The thicknessand chemical composition of the gate dielectric may vary widely withinthe scope of the present invention.

[0062] Wafer 102 with polysilicon 518 over the surface thereof isplanarized, typically by chemical mechanical polishing (CMP). The CMPoperation uses damascene layer 504 as a polish stop. The results of theCMP operation, shown in FIG. 10, illustrate newly formed gate electrode520.

[0063]FIG. 11 shows the structure of FIG. 10 after the removal ofdamascene layer 504, etch stop layer 502, and first spacer 508. Moreparticularly, FIG. 11 shows polysilicon gate electrode 520 disposedsuperjacent gate dielectric 511, which is formed over the surface of therecessed channel as shown in the figure.

[0064]FIG. 12 shows the structure of FIG. 11, after conventionalsemiconductor processing operations are used to implant source/drainextensions 524, self-aligned to gate electrode 520, form sidewallspacers 110, implant deep source/drains 522, and form silicide regions106 and 107.

[0065] An alternative embodiment is described in conjunction with FIGS.5-7 and 13-17. In this alternative illustrative embodiment, theprocessing operations as described above in connection with FIGS. 5-7are performed as before. However, referring to FIG. 13, rather thananisotropically etching the exposed silicon surface, the exposed siliconsurface is first oxidized, and then the oxidized silicon is removed,resulting in a recess 612 having a bottom portion 614 and taperedsidewalls 616.

[0066]FIG. 14 shows the structure of FIG. 13, after the furtherprocessing operations of forming a gate dielectric layer 611 over abottom portion 614 and tapered sidewalls 616 of recess 612. Gatedielectric 611 is typically formed by oxidizing the exposed siliconsurfaces of recess 612. Those skilled in the art and having the benefitof this disclosure will recognize, that gate dielectric layer 611 may beformed in other ways or with other materials. The thickness and chemicalcomposition of the gate dielectric may vary widely within the scope ofthe present invention.

[0067]FIG. 15 shows the structure of FIG. 14, after the furtherprocessing operations of forming individual gate electrodes 620 byremoving the excess polysilicon. Gate electrode 620 is formed frompolysilicon 618 by a CMP operation with damascene layer 504 acting asthe polish stop layer. CMP of polysilicon is a well-known processoperation in this field. FIG. 16 shows the structure of FIG. 15, afterdamascene layer 504, etch stop layer 502, and first spacer layer 508 areremoved by etching. As can be seen, polysilicon gate electrode 620 isdisposed superjacent gate dielectric 611, which is formed over thesurface of the recessed channel as shown in the figure.

[0068]FIG. 17 shows the structure of FIG. 16, after conventionalsemiconductor processing operations are used to implant source/drainextensions 624, self-aligned to gate electrode 620, form sidewallspacers 110, implant deep source/drains 622, and form silicide regions106 and 107.

[0069] A further alternative embodiment is described in conjunction withFIGS. 5-7 and 18-22. In this alternative illustrative embodiment, theprocessing operations as described above in connection with FIGS. 5-7are performed as before. However, referring to FIG. 18, in thisembodiment the exposed silicon surface is isotropically etched,resulting in a recess 712 having a curvilinear surface 714.

[0070]FIG. 19 shows the structure of FIG. 18, after the furtherprocessing operations of forming a gate dielectric layer 711 overcurvilinear surface 714 of recess 712, the removal of second spacer 510and the deposition of polysilicon layer 718. Gate dielectric 711 istypically formed by oxidizing the exposed silicon surface of recess 712.Those skilled in the art and having the benefit of this disclosure willrecognize, that gate dielectric layer 711 may be formed in other ways orwith other materials. The thickness and chemical composition of the gatedielectric may vary widely within the scope of the present invention.

[0071]FIG. 20 shows the structure of FIG. 19, after the furtherprocessing operations of forming individual gate electrodes 720 byremoving the excess polysilicon. Gate electrode 720 is formed frompolysilicon 718 by a CMP operation with damascene layer 504 acting asthe polish stop layer. CMP of polysilicon is a well-known processoperation in this field. FIG. 21 shows the structure of FIG. 20, afterdamascene layer 504, etch stop layer 502, and first spacer layer 508 areremoved by etching. As can be seen, polysilicon gate electrode 720 isdisposed superjacent gate dielectric 711, which is formed over thesurface of the recessed channel as shown in the figure.

[0072]FIG. 22 shows the structure of FIG. 21, after conventionalsemiconductor processing operations are used to implant source/drainextensions 705, self-aligned to gate electrode 720, form sidewallspacers 110, implant deep source/drains 704, and form silicide regions106 and 107.

[0073] In a further alternative, channel implants, typically performedprior to the formation of damascene layer 504, are performed afterdamascene layer 504, and etch stop layer 502 are patterned, and firstand second spacers 508, 510 are formed along the sidewalls of theopenings in damascene layer 504. As will be understood by those skilledin this field, by having the channel implant self-aligned to thetransistor gate, junction capacitance is reduced, and, depending on theactual doping profiles of the channel implant, source/drain extensionimplant, and deep source/drain implant, counterdoping effects may alsobe reduced.

[0074]FIG. 23 is a flow diagram illustrating a process flow inaccordance with the present invention. Openings are patterned, typicallywith conventional lithography techniques, in a damascene layer disposedon a wafer (block 2302). Spacers are then formed along the sidewalls ofthe openings in the damascene layer (block 2304). Typically a firstspacer layer, such as an oxide of silicon, is formed and a second spacerlayer, typically a nitride of silicon, is formed adjacent to the firstspacer layer. A recess is then formed at the locations defined by theopenings (block 2306). The specific shape of the recesses may be variedwithin the scope of the present invention. For example, recesses may beshaped rectangularly, trapezoidally, curvilinearly, and so on. Thevarious shapes may be achieved by applying corresponding various etchtechniques. Isotropic and anisotropic etching are two examples. A gatedielectric is then formed over the recess (block 2308) and a gateelectrode is formed over the gate dielectric (block 2310). Source/drainextensions are formed, typically by ion implantation, self-aligned tothe gate electrode (block 2312).

[0075] Conclusion

[0076] Embodiments of the present invention advantageously provide afield effect transistor structure having very short channel length andrelatively low source/drain extension resistivity without the adverseshort channel effects of conventional MOSFETs having equivalent channellengths and source/drain extension resistivities. Embodiments of thepresent invention have source/drain extensions that are elevatedrelative the channel region of a MOSFET.

[0077] A further advantage of particular embodiments of the presentinvention is reduced parasitic junction capacitance resulting fromperforming the channel implant only into portions of the wafer that willbecome the channel regions of transistors.

[0078] Those skilled in the art and having the benefit of thisdisclosure will recognize that although field oxide regions are notshown in the Figures, the operations and structures shown and describedherein, are compatible with various field oxide isolation architectures.Examples of field oxide isolation architectures include shallow trenchisolation regions in a surface of a substrate, and the older localoxidation of silicon, which often formed non-planarized oxide isolationregions.

[0079] It will be understood by those skilled in the art having thebenefit of this disclosure that many design choices are possible withinthe scope of the present invention. For example, structural parameters,including but not limited to, gate insulator thickness, gate insulatormaterials, gate electrode thickness, sidewall spacer material,inter-layer dielectric material, isolation trench depth, and S/D andwell doping concentrations may all be varied from that shown ordescribed in connection with the illustrative embodiments.

[0080] It will be understood that various other changes in the details,materials, and arrangements of the parts and steps which have beendescribed and illustrated may be made by those skilled in the art havingthe benefit of this disclosure without departing from the principles andscope of the invention as expressed in the subjoined claims.

What is claimed is:
 1. A field effect transistor, comprising: asubstrate having a recess in a surface thereof, the recess having abottom portion and substantially vertical sidewalls; a gate dielectriclayer disposed superjacent the bottom portion of the recess and adjacentthe substantially vertical sidewalls; a gate electrode overlying thegate dielectric layer; and source/drain terminals disposed in thesubstrate in alignment with a pair of laterally opposed gate electrodesidewalls; wherein the source/drain terminals have an extension whichextends downwardly, from approximately the surface of the substrate,along the sidewalls of the recess.
 2. The transistor of claim 1 ,further comprising a portion of the gate electrode that overlies aninnermost portion of the source/drain extension:
 3. The structure ofclaim 2 , wherein the gate electrode conforms to the recessed channel.4. A field effect transistor, comprising: a substrate having a recess ina surface thereof, the recess having bottom portion and taperedsidewalls, the tapered sidewall surfaces forming an obtuse angle withrespect to the bottom portions of the recess; a gate dielectric layerdisposed superjacent the bottom portion of the recess and adjacent thetapered sidewalls; a gate electrode overlying the gate dielectric layer;and source/drain terminals disposed in the substrate in alignment with apair of laterally opposed gate electrode sidewalls; wherein thesource/drain terminals have an extension which extends downwardly, fromapproximately the surface of the substrate, along the sidewalls of therecess.
 5. The transistor of claim 4 , wherein a portion of the gateelectrode that overlies an innermost portion of the source/drainextension.
 6. The transistor of claim 4 , wherein the gate electrodeconforms to the recessed channel.
 7. A field effect transistor,comprising: a substrate having a recess in a surface thereof, the recesshaving a curvilinear shape; a gate dielectric layer disposed superjacentthe curvilinear recess; a gate electrode overlying the gate dielectriclayer; and source/drain terminals disposed in the substrate in alignmentwith a pair of laterally opposed gate electrode sidewalls; wherein thesource/drain terminals have an extension which extends downwardly, fromapproximately the surface of the substrate, along the curvilinear sidesof the recess.
 8. The transistor of claim 6 , wherein a portion of thegate electrode that overlies an innermost portion of the source/drainextension.
 9. The transistor of claim 6 , wherein the gate electrodeconforms to the recessed channel.
 10. A method of making amicroelectronic device, comprising: forming a first layer over asubstrate; forming openings in the first layer, the openings exposing aportion of the substrate, the openings having substantially verticalsidewalls; forming a first spacer adjacent the sidewalls of the firstlayer openings; forming a second spacer adjacent the first spacer;etching a portion of the exposed substrate; removing the second spacer;forming a dielectric layer superjacent the exposed portions of thesubstrate; forming an electrode superjacent the dielectric layer; andremoving the first layer.
 11. The method of claim 10 , wherein etching aportion of the exposed substrate comprises isotropically etching thesubstrate.
 12. The method of claim 10 , wherein etching a portion of theexposed substrate comprises anisotropically etching the substrate. 13.The method of claim 10 , further comprising oxidizing the exposedportions of the substrate, and wherein the etching a portion of theexposed substrate comprises etching the oxidized portions of thesubstrate.
 14. A method of forming a field effect transistor,comprising: depositing an etch stop layer and a damascene layer over asilicon substrate; removing portions of the damascene and etch stoplayers to expose portions of the silicon, and form sidewalls in thedamascene and etch stop layers; forming a first spacer layer along thesidewalls of the damascene layer and the etch stop layer; etching theexposed silicon; removing the second spacer; forming a gate dielectriclayer superjacent the etched silicon; and depositing a gate electrodelayer over the damascene and gate dielectric layers; planarizing thegate electrode layer so as to form a gate electrode; removing thedamascene, second spacer, and etch stop layers; and forming source/drainterminals self-aligned to the gate electrode.
 15. The method of claim 14, wherein planarizing the gate electrode layer comprises chemicalmechanical polishing using the damascene layer as a polish stop.
 16. Themethod of claim 14 , further comprising implanting ions into the siliconsubstrate.
 17. The method of claim 14 , further comprising implantingions into the silicon substrate, after the first and second spacers areformed.
 18. The method of claim 14 , further comprising performing achannel implant into the silicon using the damascene, first spacer, andsecond spacer layers as implant masks.
 19. The method of claim 14wherein forming source/drain terminals comprises implanting ions of afirst conductivity type into the silicon, adjacent to the gateelectrode; forming third spacers adjacent to the gate electrode, andimplanting ions of a first conductivity type into the silicon, adjacentto the third spacers.
 20. The method of claim 14 , wherein etching thesilicon comprises an anisotropic etch.
 21. The method of claim 14 ,wherein etching the silicon comprises an isotropic etch.
 22. A method offorming a field effect transistor, comprising: depositing an etch stoplayer and a damascene layer over a silicon substrate; removing portionsof the damascene and etch stop layers to expose portions of the silicon,and form sidewalls in the damascene and etch stop layers; forming afirst spacer layer along the sidewalls of the damascene layer and theetch stop layer, and a second spacer adjacent the first spacer layer;oxidizing the exposed silicon; etching the exposed oxidized silicon;removing the second spacer; forming a gate dielectric layer superjacentthe etched silicon; and depositing a gate electrode layer over thedamascene and gate dielectric layers; planarizing the gate electrodelayer so as to form a gate electrode; removing the damascene, secondspacer, and etch stop layers; and forming source/drain terminalsself-aligned to the gate electrode.